Parallel realizations of distributed sample scramblers for applications to cell-based ATM transmission

In this paper, a theory is developed in support of parallel realizations of the distributed sample scramblers (DSS) in the cell-based ATM transmission environment. For the relevant parallel realizations of the SRG (shift register generator) engines and the SRG sequence-generating circuits, the PSRG theory is applied which is readily available for parallel FSS (frame synchronous scrambler). For the synchronization of the parallel DSS, the double-sampling and double-correction schemes are employed as they efficiently match the two adjacently located sample conveyance channels within the ATM cells. The resulting synchronization conditions are described in terms of three theorems—one regarding the sampling time and vector’s condition, and the other two regarding the correction time and vector’s conditions for evenand odd-lengthed SRG’s. Demonstration is given at the end on the use of the developed theory for parallel realizations of DSS in scrambling and descrambling the ITU-T recommended cell-based ATM signals.